Mastering Advanced RTL Design u0026 Verification Concepts: An Expert Challenge Quiz

1. Hazard Identification in Synchronous Design

   In a complex synchronous digital circuit, which mechanism is MOST effective in mitigating the impact of both setup and hold timing violations that may arise due to clock skew between registers?

   1. A. Adding pipeline registers to balance path delays
   2. B. Using asynchronous resets at every stage
   3. C. Increasing the clock frequency beyond specification
   4. D. Employing level-sensitive latches throughout the design
   5. E. Disabling retiming during synthesis

2. Assertion-Based Verification Nuances

   When using assertion-based verification for a bus protocol, what is the main advantage of temporal assertions like 'eventually' or 'always' compared to only value-based checks? Example: Checking that every bus request is eventually granted.

   1. A. Temporal assertions detect only combinational errors
   2. B. They enable property checking across multiple clock cycles
   3. C. They require less memory than value-based assertions
   4. D. Temporal assertions are evaluated only once at simulation start
   5. E. They automatically generate formal proofs for functional coverage

3. Coverage Closure in Constrained-Random Verification

   During constrained-random verification of an ALU, the functional coverage reports that certain corner cases, such as multiplication with negative operands, are never hit. Which strategy is MOST effective in systematically closing this coverage gap?

   1. A. Increasing simulation runtime without modifying constraints
   2. B. Widening constraints to allow more legal stimulus variation
   3. C. Manually editing the coverage database to mark points as covered
   4. D. Commenting out coverage points that are hard to hit
   5. E. Reducing randomization seed width to repeat tests

4. Formal Verification and State Space Explosion

   A formal verification tool reports 'state space explosion' when verifying a large register file with multiple read/write ports. What is the MOST effective technique to manage this complexity and successfully complete verification?

   1. A. Increasing simulation clock periods
   2. B. Performing modular verification by abstracting unused ports
   3. C. Disabling parameterization in the register file design
   4. D. Randomly pruning unreachable states from the design
   5. E. Reducing the register width in the HDL code

5. Clock Domain Crossing Bugs

   If a designer uses a single D flip-flop to transfer a signal from one clock domain to another asynchronous clock domain, what is the specific risk introduced, and what is the recommended solution?

   1. A. The signal can be lost due to priority inversion; recommended: use a rising-edge detector
   2. B. The data may be metastable; recommended: employ a two-stage synchronizer
   3. C. The clock can glitch; recommended: use a clock buffer
   4. D. The logic can delay; recommended: use an asynchronous FIFO
   5. E. The output can tri-state; recommended: add a pull-down resistor