Essential Concepts in Computer Architecture Quiz

Explore fundamental topics in computer architecture with these easy, examiner-style questions. Assess your understanding of core principles such as CPU components, instruction pipelines, cache memory, and parallelism.

1. CPU Components

   Which component of the CPU is primarily responsible for performing arithmetic and logical operations?

   1. Register
   2. Arithmetic Logic Unit (ALU)
   3. Control Unit (CU)
   4. Cache

   Explanation: The ALU performs arithmetic and logical operations, making it the correct answer. The Control Unit directs operations but does not perform calculations. Registers store data temporarily, and cache is used for fast data access but not calculations.

2. Memory Hierarchy

   Which of the following types of memory is closest to the CPU in terms of access speed?

   1. Cache
   2. Main Memory (RAM)
   3. Hard Disk Drive
   4. Flash Storage

   Explanation: Cache is the fastest and located nearest to the CPU, providing quick access to frequently used data. Main memory (RAM) is slower and further away. Hard disk drives and flash storage are used for long-term storage and are much slower.

3. Instruction Pipeline

   In a classic 5-stage instruction pipeline, what is the primary purpose of the decode stage?

   1. Write the result back to the register
   2. Fetch the instruction from memory
   3. Interpret the instruction and prepare necessary control signals
   4. Execute the instruction's operation

   Explanation: The decode stage interprets the instruction and sets up signals for execution. Fetch retrieves the instruction; execute performs its operation; write-back stores results. Only the listed answer describes decoding.

4. Cache Mapping Types

   Which cache mapping technique uses a simple direct relationship between memory blocks and cache lines?

   1. Random-mapped
   2. Direct-mapped
   3. Set-associative
   4. Fully associative

   Explanation: Direct-mapped cache assigns each memory block to exactly one cache line. Fully associative allows any block to any line, set-associative is a mix of both, and random-mapped is not a standard term.

5. RISC vs CISC

   Which statement accurately describes a characteristic of a RISC architecture?

   1. Instructions vary greatly in size and complexity
   2. Heavily relies on microcoding for instruction execution
   3. Uses a small, fixed set of simple instructions
   4. Allows very complex instructions with multiple cycles

   Explanation: RISC architectures focus on a small, uniform set of simple instructions. Complex instructions, variable instruction sizes, and microcoding are characteristics more typical of CISC architectures.

6. Parallelism Concept

   What type of parallelism is exploited when a single instruction operates on multiple data elements at once?

   1. SISD (Single Instruction Single Data)
   2. MISD (Multiple Instruction Single Data)
   3. SIMD (Single Instruction Multiple Data)
   4. MIMD (Multiple Instruction Multiple Data)

   Explanation: SIMD executes one instruction on several data points simultaneously, common in multimedia and scientific computing. MIMD uses different instructions and data; SISD has no parallelism; MISD is rare and typically theoretical.

7. Bus Systems

   In computer architecture, which bus is mainly responsible for carrying addresses from the CPU to memory?

   1. Data bus
   2. Address bus
   3. Control bus
   4. Expansion bus

   Explanation: The address bus transmits memory addresses from the CPU, letting memory know where to deliver data. The data bus sends actual data, the control bus carries signals, and the expansion bus connects additional peripherals.

8. Interrupts

   What is the primary purpose of hardware interrupts in a computer system?

   1. Alert the CPU to urgent events, temporarily halting current execution
   2. Switch the CPU into sleep mode
   3. Increase CPU clock speed for intensive tasks
   4. Provide persistent data storage

   Explanation: Hardware interrupts inform the CPU of urgent events, causing it to pause and address the new event. They do not directly alter clock speed, store data, or manage CPU sleep states.

9. Von Neumann Architecture

   Which feature is characteristic of the Von Neumann architecture model?

   1. Separate buses for data and instructions
   2. In-built parallel execution units
   3. Custom processor for graphics operations
   4. Shared bus for both data and instructions

   Explanation: Von Neumann architecture uses a single bus for data and instructions, leading to the 'Von Neumann bottleneck.' Harvard architecture uses separate buses, and the other options are unrelated.

10. Secondary Storage

    Which of the following is considered secondary storage in computer architecture?

    1. Address bus
    2. Level 1 cache
    3. Solid State Drive (SSD)
    4. CPU register

    Explanation: An SSD is a type of secondary storage for long-term data retention. Registers and cache are primary, volatile storage within the CPU, and the address bus is not storage at all.